Digital Voice Systems VC-20-ATC-10B Especificaciones descargar pdf (Pagina 40)

FAA20 Embedded NEXCOM Vocoder

Board Manual

This manual has been prepared for the Federal Aviation Administration.

FA100-00107 (March 2004) – Rev 1.0.0 Page 34

6.0 ARCHITECTURAL DESCRIPTION

This section provides an architectural overview of the FAA20. The

following topics are included:

• Hardware Architecture. Provides a hardware block diagram and

memory maps.

• Software Architecture. Provides a software block diagram and a

description of software tasks and interrupts. Also discusses queues,

packets and data management.

6.1 Hardware Architecture

This section presents an overview of the FAA20 hardware design and

includes a set of memory maps.

6.1.1 Hardware Block Diagram

The FAA20 hardware design is based on a TI DSP processor, i.e., the

TMS320VC5416. This processor is required in order to execute the DVSI

optimized software vocoder written in C54x assembly. Figure 15 is a block

diagram of the FAA20 hardware.

The FAA20 supports three voice interfaces: an analog voice interface

(AUD), a digital PCM interface (PCM), and a compressed nibble interface

(NIB).

The analog voice interface is provided by a TI PCM3500 16-bit linear voice

codec. The codec is configured to sample analog voice at either a 8 ksps

(normal timing) or a 6.67 ksps (truncated timing) rate. External operational

amplifiers enable the FAA20 to drive loads as low as 8 ohms. Feedback

components in the front end circuit form a third-order low pass filter used to

band limit the analog voice signal (100 to 3700 Hz). The codec connects to

a DSP multi-channel buffered serial port (MCBSP) and serially shifts data

into and out of the DSP.

The digital PCM interface is used to serially shift data samples directly into

and out of the DSP via MCBSP #1. While not shown in the figure, the

signals are actually buffered through a 5V complex programmable logic

device (CPLD) to provide TTL compatible signaling. The serial port

requires a clock and frame synchronization signals to control data flow.

The frame synchronization signal also functions as a time slot enable signal

for a multi-drop time division multiplexed serial bus.

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Digital Voice Systems VC-20-ATC-10B Especificaciones Pagina 40