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AMBE-3000F™ Vocoder Chip Users Manual

Version 3.4, April, 2014

ardware Information

PPT_

DATA2 35 N3 I/O Parallel Packet Data

PPT_DATA3 36 P3 I/O Parallel Packet Data

PPT_DATA4 37 L4 I/O Parallel Packet Data

PPT_DATA5 38 M4 I/O Parallel Packet Data

PPT_DATA6 40 K5 I/O Parallel Packet Data

PPT_DATA7 41 N5 I/O Parallel Packet Data

PKT_RX_WAKE 43 M5 Input

When the UART interface is used and low-power mode is enabled,

this pin must be connected to UART_RX. When the McBSP

packet interface is used this signal should be connected to the

inverted McBSP_FSR signal.

STANDBYn 44 M6 Output

For debugging purposes only. This signal is low while the AMBE-

3000F™ Vocoder Chip is in standby mode. Standby mode is

entered only when Low power mode is enabled and there is no

activity.

IDLEn 45 P6 Output

For debugging purposes only. This signal is low while the AMBE-

3000F™ Vocoder Chip is in Idle mode. Idle mode is entered when

there is no activity and low power mode is disabled.

PPT_READ 46 N6 Input Read data from PACKET_DATA pins

PPT_WRITE 47 L6 Input Write data to PACKET_DATA pins

PPT_ACK 48 K7 Output

Used to Acknowledges the transitions of PPT_READ and

PPT_WRITE

3v3FL 52 N8 PWR

3.3-V Flash Core Power Pin. This pin should be connected to 3.3

V at all times after power-up sequence requirements have been

met.

X2 57 M9 Output

Output from internal oscillator for use with a crystal. If the internal

oscillator is not used this pin should be unconnected.

X1/XCLKIN 58 K9 Input

29.4912 MHz Clock input. The AMBE-3000 may be operated

using the internal oscillator by connecting a crystal between X1

and X2 or with an external clock source. The AMBE-3000F™

Vocoder Chip can be operated with an external clock source,

provided that the proper voltage levels are driven on the

X1/XCLKIN pin. It should be noted that the X1/XCLKIN pin is

referenced to the 1.8-V core digital power supply (VDD), rather

than the 3.3-V I/O supply (VDDIO). A clamping diode may be

used to clamp a buffered clock signal to ensure that the logic-high

level does not exceed VDD (1.8 V) or a 1.8-V oscillator may be

used.

CODEC_RESETn 60 P10 Output Output to Reset the Codec. This signal is active low.

RUNn 61 P11 Output

For debugging purposes only. This signal is low while the either

encoder or decoder is executing otherwise it is high.

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